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LTC4305 2-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering
FEATURES

DESCRIPTIO

1:2 2-Wire Multiplexer/Switch Connect SDA and SCL Lines with 2-Wire Bus Commands Supply Independent Bidirectional Buffer for SDA and SCL Lines Increases Fan-Out Programmable Disconnect from Stuck Bus Compatible with I2C and SMBus Standards Rise Time Accelerator Circuitry SMBus Compatible ALERT Response Protocol Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane 10kV Human Body Model ESD Ruggedness 16-Lead (4mm x 5mm) DFN and SSOP Packages
The LTC(R)4305 is a 2-channel, 2-wire bus multiplexer with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Through software control, the LTC4305 connects the upstream 2-wire bus to any desired combination of downstream channels. Each channel can be pulled up to a supply voltage ranging from 2.2V to 5.5V, independent of the LTC4305 supply voltage. The downstream channels are also provided with an ALERT1-ALERT2 inputs for fault reporting. Programmable timeout circuitry disconnects the downstream buses if the bus is stuck low. When activated, rise time accelerators source currents into the 2-wire bus pins to reduce rise time. Driving the ENABLE pin low restores all features to their default states. Three address pins provide 27 distinct addresses. The LTC4305 is available in 16-lead (4mm x 5mm) DFN and SSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending.
APPLICATIO S

Nested Addressing 5V/3.3V Level Translator Capacitance Buffer/Bus Extender
TYPICAL APPLICATIO
2.5V 3.3V
A Level-Shifting and Nested Addressing Application I2C Bus Waveforms
0.01F 10k 10k 10k VCC SCLIN MICROCONTROLLER SDAIN ALERT SCL1 SDA1 ALERT1 5V LTC4305 ADR2 ADR1 ADR0 GND SCL2 SDA2 ALERT2
4305 TA01
VCC = 3.3V
10k 10k 10k
SCLIN 2V/DIV
SFP MODULE #1 ADDRESS = 1111 000
SCL1 2V/DIV
10k
10k
10k SFP MODULE #2 ADDRESS = 1111 000
SCL2 2V/DIV 500ns/DIV
ADDRESS = 1000 100
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VBACK = 2.5V VCARD1 = 3.3V VCARD2 = 5V
4305 TA01b
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LTC4305
ABSOLUTE
AXI U RATI GS (Note 1)
Operating Temperature Range LTC4305C ............................................... 0C to 70C LTC4305I ............................................. -40C to 85C Storage Temperature Range DHD Package .................................... -65C to 125C GN Package ....................................... -65C to 150C Lead Temperature (Soldering, 10 sec) GN Package ...................................................... 300C
Supply Voltage (VCC) ................................... -0.3V to 7V Input Voltages (ADR0, ADR1, ADR2, ENABLE, ALERT1, ALERT2) .................... -0.3V to 7V Output Voltages (ALERT, READY) ............... -0.3V to 7V Input/Output Voltages (SDAIN, SCLIN, SCL1, SDA1, SCL2, SDA2) ...................... -0.3V to 7V Output Sink Current (SDAIN, SCLIN, SCL1, SDA1, SCL2, SDA2, ALERT, READY) ............... 10mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW ALERT2 ALERT SDAIN GND SCLIN ENABLE VCC ADRO 1 2 3 4 5 6 7 8 17 16 SCL2 15 SDA2 14 ALERT1 13 SDA1 12 SCL1 11 READY 10 ADR2 9 ADR1
DHD PACKAGE 16-LEAD (4mm x 5mm) PLASTIC DFN
EXPOSED PAD (PIN 17) PCB CONNECTION OPTIONAL MUST BE CONNECTED TO PCB TO OBTAIN JA = 43C/W OTHERWISE JA = 140C/W. TJMAX = 125C
ORDER PART NUMBER LTC4305CDHD LTC4305IDHD
DHD PART MARKING 4305 4305
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marketing: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC ICC ICC ENABLE = 0V VUVLOU VUVLOHYST PARAMETER Input Supply Range Input Supply Current Input Supply Current UVLO Upper Threshold Voltage UVLO Threshold Hysteresis Voltage Power Supply/Start-Up
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
CONDITIONS
Downstream Connected, VCC = 5.5V SCL Bus Low, SDA Bus High VENABLE = 0V, VCC = 5.5V
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TOP VIEW ALERT2 ALERT SDAIN GND SCLIN ENABLE VCC ADR0 1 2 3 4 5 6 7 8 16 SCL2 15 SDA2 14 ALERT1 13 SDA1 12 SCL1 11 READY 10 ADR2 9 ADR1
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 125C, JA = 135C/W
ORDER PART NUMBER LTC4305CGN LTC4305IGN
GN PART MARKING 4305 4305I
MIN 2.7
TYP
MAX 5.5
UNITS V mA mA V mV
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5.2 1.25 2.3 100 2.5 175
8 2.5 2.7 250
LTC4305
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
SYMBOL VTH EN VEN HYST tPHL EN tPLH EN IIN EN VLOW READY IOFF READY ALERT VALERT(OL) IOFF, ALERT IIN, ALERT1-2 VALERT1-2(IN) VALERT1-2(HY) ALERT Output Low Voltage ALERT Off State Input Leakage Current ALERT1-ALERT2 Input Current ALERT1-ALERT2 Pin Input Falling Threshold Voltages ALERT1-ALERT2 Pin Input Threshold Hysteresis Voltages Initial Slew Requirement to Activate Rise Time Accelerator Currents Rise Time Accelerator DC Threshold Voltage Rise Time Accelerator Pull-Up Current SDAIN, SCLIN, SDA1-2, SCL1-2 Pins SDAIN, SCLIN, SDA1-2, SCL1-2 Pins SDAIN, SCLIN, SDA1-2, SCL1-2 Pins (Note 3) VCC = 2.7V, 5.5V TIMSET1,0 = 01 TIMSET1,0 = 10 TIMSET1,0 = 11

ELECTRICAL CHARACTERISTICS
PARAMETER ENABLE Falling Threshold Voltage ENABLE Threshold Hysteresis Voltage ENABLE Delay, On-Off ENABLE Delay, Off-On ENABLE Input Leakage Current READY Pin Logic Low Output Voltage READY Off State Input Leakage Current
CONDITIONS
MIN 0.8
TYP 1.0 60 60 20
MAX 1.2
UNITS V mV ns ns
Power Supply/Start-Up
VENABLE = 0V, 5.5V, VCC = 5.5V IPULL-UP = 3mA, VCC = 2.7V VREADY = 0V, 5.5V, VCC = 5.5V IALERT = 3mA, VCC = 2.7V VALERT = 0V, 5.5V VALERT1-2 = 0V, 5.5V

0.1 0.18 0 0.2 0 0 0.8 1.0 80
1 0.4 1 0.4 1 1 1.2
A V A V A A V mV
Rise Time Accelerators VSDA,SCL slew VRISE,DC IBOOST 0.4
0.8 1
V/s V mA
0.7
0.8 5.5
4
Stuck Low Timeout Circuitry VTIMER(L) VTIMER(HYST) TTIMER1 TTIMER2 TTIMER3 VOS,BUF VOS,UP-BUF VOS,DOWN-BUF VOL VOL VIL,MAX VTHSDA,SCL ILEAK Stuck Low Falling Threshold Voltage Stuck Low Threshold Hysteresis Voltage Timeout Time #1 Timeout Time #2 Timeout Time #3 Buffer Offset Voltage Upstream Buffer Offset Voltage VIN,BUFFER = 0V Downstream Buffer Offset Voltage VIN,BUFFER = 0V Output Low Voltage, VIN,BUFFER = 0V Output Low Voltage, VIN,BUFFER = 0.2V Buffer Input Logic Low Voltage Downstream SDA, SCL Logic Threshold Voltage Input Leakage Current SDA, SCL Pins; VCC = 0 to 5.5V; Buffers Inactive 25 12.5 6.25 25 40 70 60 80 0.4 0.52 80 30 15 7.5 60 80 110 110 140 35 17.5 8.75 100 120 150 160 200 400 320 0.4 0.8 0.52 1.0 0.64 1.2 5 0.64 V mV ms ms ms mV mV mV mV mV mV mV V V A
Upstream-Downstream Buffers RBUS = 10k, VCC = 2.7V, 5.5V (Note 4) VCC = 2.7V, RBUS = 2.7k (Note 4) VCC = 5.5V, RBUS = 2.7k (Note 4) VCC = 2.7V, RBUS = 2.7k (Note 4) VCC = 5.5V, RBUS = 2.7k (Note 4) SDA, SCL Pins; ISINK = 4mA, VCC = 3V, 5.5V SDA, SCL Pins; ISINK = 500A, VCC = 2.7V, 5.5V VCC = 2.7V, 5.5V

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LTC4305
The denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V unless otherwise noted.
SYMBOL I2C Interface VADR(H) VADR(L) IADR(IN, L) IADR(IN, H) IADR,FLOAT VSDAIN,SCLIN(TH) VSDAIN,SCLIN(HY) ISDAIN,SCLIN(OH) CIN VSDAIN(OL) I2C Interface Timing fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DATI tHD, DATO tSU, DAT tf tSP Maximum SCL Clock Frequency Bus Free Time Between Stop/Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Set-Up Time Stop Condition Set-Up Time Data Hold Time Input Data Hold Time Output Data Set-Up Time SCL, SDA Fall Times Pulse Width of Spikes Suppressed by the Input Filter (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 20 + 0.1 * CBUS 50 150 300 400 0.75 45 -30 -30 -25 600 50 1.3 100 0 0 0 900 100 300 250 kHz s ns ns ns ns ns ns ns ns ADR0-2 Input High Voltage ADR0-2 Input Low Voltage ADR0-2 Logic Low Input Current ADR0-2 Logic High Input Current ADR0-2 Allowed Input Current SDAIN, SCLIN Input Falling Threshold Voltages SDAIN, SCLIN Hysteresis SDAIN, SCLIN Input Current SDA, SCL Input Capacitance SDAIN Output Low Voltage SCL, SDA = VCC (Note 2) ISDA = 4mA, VCC = 2.7V

ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS V V A A A V mV A pF V
0.75 * VCC 0.9 * VCC 0.1 * VCC 0.25 * VCC -30 30 5 1.4 -60 60 13 1.6 30 5 6 0.2 10 0.4 1.8 -80 80
ADR0-2 = 0V, VCC = 5.5V ADR0-2 = VCC = 5.5V VCC = 2.7V, 5.5V (Note 5) VCC = 5.5V

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design and not subject to test, unless stated otherwise in the Conditions. Note 3: The boosted pull-up currents are regulated to prevent excessively fast edges for light loads. See the Typical Performance Characteristics for rise time as a function of VCC and parasitic bus capacitance CBUS and for IBOOST as a function of VCC and temperature.
Note 4: When a logic low voltage VLOW is forced on one side of the upstream-downstream buffers, the voltage on the other side is regulated to a voltage VLOW2 = VLOW + VOS is a positive offset voltage. VOS,DOWN-BUF is the offset voltage when the LTC4305 is driving the upstream pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the LTC4305 is driving the downstream pin (e.g., SDA1). See the Typical Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a function of VCC and bus pull-up current. Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage currents up to IADR,FLOAT and still convert the address correctly.
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LTC4305 TYPICAL PERFOR A CE CHARACTERISTICS
Buffer Circuitry tPHL vs Temperature
120 100 VCC = 3.3V
tPHL (ns)
VCC = 5V 60 40 20 0 -50 -25
RISE TIME (ns)
150
VCC = 5V
CURRENT (mA)
80
50 25 75 0 TEMPERATURE (C)
VOS,UP-BUF vs Bus Pull-Up Current
180 160 250 140 120 VCC = 3.3V VCC = 5V 200 300
VOS (mV)
VOS (mV)
100 80 60 40 20 0 0 3 1 2 BUS PULL-UP CURRENT (mA) 4
4305 G04
Downstream RFET on Resistance vs VCC and Temperature
45 40 35 VCC = 3.3V 25 20 15 10 5 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
2 14 12
IBOOST (mA)
30
RON ()
UW
100
4305 G01
(TA = 25C unless otherwise specified.)
Rise Time vs CBUS vs VCC
250 dV = 0.3V * VCC TO 0.7V * VCC RBUS = 10k VCC = 3.3V
ICC vs Temperature
6 VCC = 5V 5 4 3 2 1 0 -50 -25 UPSTREAM CONNECTED TO CHANNEL 1, SCL BUS LOW, SDA BUS HIGH 50 25 75 0 TEMPERATURE (C) 100 125 VCC = 3.3V
200
100
50
125
0
0
200 600 800 400 CAPACITANCE, CBUS (pF)
1000
4305 G02
4305 G03
VOS,DOWN-BUF vs Bus Pull-Up Current
VCC = 3.3V 150 VCC = 5V 100 50 0 0 1 2 3 BUS PULL-UP CURRENT (mA) 4
4305 G05
IBOOST vs Temperature
VCC = 5V 10 8 6 VCC = 3.3V 4
VCC = 5V
0 -50 -25
0 25 50 75 TEMPERATURE (C)
100
125
4305 G06
4305 G07
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LTC4305
PI FU CTIO S
ALERT1-ALERT2 (Pins 14, 1): Fault Alert Inputs, Channels 1-2. Devices on each of the two output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4305 then pulls the ALERT low to pass the fault indication on to the host. See the "Operation" section below for the details of how ALERT is set and cleared. Connect unused fault alert inputs to VCC. ALERT (Pin 2): Fault Alert Output. An open-drain output that is pulled low when a fault occurs to alert the host controller. The LTC4305 pulls ALERT low when any of the ALERT1-ALERT2 pins is low; when the two-wire bus is stuck low; or when the Connection Requirement bit of register 2 is low and a master tries to connect to a downstream channel that is low. See the "Operation" section below for the details of how ALERT is set and cleared. The LTC4305 is compatible with the SMBus Alert Response Address protocol. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused. SDAIN (Pin 3): Serial Bus Data Input and Output. Connect this pin to the SDA line on the master side. An external pull-up resistor or current source is required. GND (Pin 4): Device Ground. SCLIN (Pin 5): Serial Bus Clock Input. Connect this pin to the SCL line on the master side. An external pull-up resistor or current source is required. ENABLE (Pin 6): Digital Interface Enable and Register Reset. Driving ENABLE high enables I2C communication to the LTC4305. Driving ENABLE low disables I2C communication to the LTC4305 and resets the registers to their default state as shown in the Operations section. When ENABLE returns high, masters can read and write the LTC4305 again. If unused, tie ENABLE to VCC. VCC (Pin 7): Power Supply Voltage. Connect a bypass capacitor of at least 0.01F directly between VCC and GND for best results. ADR0-ADR2 (Pins 8-10): Three-State Serial Bus Address Inputs. Each pin may be floated, tied to ground, or tied to VCC. There are therefore 27 possible addresses. See Table 1 in Applications Information section. When the pins are floated, they can tolerate 5A of leakage current and still convert the address correctly. READY (Pin 11): Connection Ready Digital Output. An N-channel MOSFET open-drain output transistor that pulls down when none of the downstream channels is connected to the upstream bus and turns off when one or more downstream channels is connected to the upstream bus. Connect a 10k resistor to a power supply voltage to provide the pull-up. Tie to ground if unused. SCL1-SCL2 (Pins 12, 16): Serial Bus Clock Outputs Channels 1-2. Connect pins SCL1-SCL2 to the SCL lines on the downstream channels 1-2, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Otherwise, an external pull-up resistor or current source is required on each pin. SDA1-SDA2 (Pins 13, 15): Serial Bus Data Output Channels 1-2. Connect pins SDA1-SDA2 to the SDA lines on downstream channels 1-2, respectively. It is acceptable to float any pin that will never be connected to the upstream bus. Otherwise, an external pull-up resistor or current source is required on each pin. Exposed Pad (Pin 17, DHD Package Only): Exposed pad may be left open or connected to device ground.
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LTC4305
BLOCK DIAGRA
INACC SLEW RATE DETECTOR SDAIN 3
INACC SLEW RATE DETECTOR SCLIN 5
READY 11 FET1 CONN FET1 SCLIN 1.6V/1.52V SDAIN FET2 ALERT 1V THRESHOLD COMPARATORS 14 ALERT1 1 ALERT2
+ - + -
100ns GLITCH FILTER
100ns GLITCH FILTER
C1 2pF
VCC 7 2.5V/2.35V ENABLE 6 1.1V/1V
+ - + -
1s FILTER
UVLO
W
UPSTREAM DOWNSTREAM BUFFERS OUTACC SLEW RATE DETECTOR 13 SDA1 15 SDA2 UPSTREAM DOWNSTREAM BUFFERS OUT ACC SLEW RATE DETECTOR 12 SCL1 STUCK LOW 0.52V COMPARATORS 16 SCL2 2 DOWNSTREAM 1V THRESHOLD COMPARATORS FET2 TIMSET1 TIMSET0 TIMEOUT_REAL TIMEOUT_LATCH VCC RLIM 50k 2 CH1CONN-CH2CONN 2-WIRE DIGITAL INTERFACE AND REGISTERS CONN_REQ CONNECTION CIRCUITRY UVLO 4 GND FAILCONN_ATTEMPT 2 BUS1_LOG-BUS2_LOG 2 PORB STUCK LOW TIMEOUT CIRCUITRY 2 AL1-AL2 2 ALERT FET1 FET2 ALERT LOGIC AL1-AL2 ADDRESS FIXED BITS "10" 5 INACC OUTACC
4305 BD
I2C ADDR
10 ADR2 5 1 OF 27 9 ADR1 8 ADR0
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LTC4305
OPERATIO
Register 0 (00h)
BIT NAME d7 Downstream Connected
Control Register Bit Definitions
Register 1 (01h)
TYPE* DESCRIPTION R Indicates if upstream bus is connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream bus connected to one or more downstream buses Logic state of ALERT1 pin, noninverting Logic state of ALERT2 pin, noninverting Not Used Not Used Indicates if an attempt to connect to a downstream bus failed because the "Connection Requirement" bit in Register 2 was low and the downstream bus was low 0 = Failed connection attempt occurred 1 = No failed attempts at connection occurred Latched bit indicating if a timeout has occurred and has not yet been cleared. 0 = no latched timeout 1 = latched timeout Indicates real-time status of Stuck Low Timeout Circuitry 0 = no timeout is occurring 1 = timeout is occurring d5-d0 Reserved BIT d7 NAME Upstream Accelerators Enable TYPE* DESCRIPTION R/W Activates upstream rise time accelerator currents 0 = upstream rise time accelerator currents inactive (default) 1 = upstream rise time accelerator currents active R/W Activates downstream rise time accelerator currents 0 = downstream rise time accelerator currents inactive (default) 1 = downstream rise time accelerator currents active R Not Used
d6 ALERT1 Logic State d5 ALERT2 Logic State d4 Reserved d3 Reserved d2 Failed Connection Attempt
d1 Latched Timeout
d0 Timeout Real Time
Note: Masters write to Register 0 to reset the fault circuitry after a fault has occurred and been resolved. Because Register 0 is Read-Only, no other functionality is affected. * For Type, "R/W" = Read Write, "R" = Read Only
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R R R R R d6 Downstream Accelerators Enable * For Type, "R/W" = Read Write, "R" = Read Only R R
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LTC4305
OPERATIO
Register 2 (02h) BIT NAME d7 Reserved d6 Reserved d5 Connection Requirement
d4 Reserved d3 Reserved d2 Mass Write Enable
d1 Timeout Mode Bit 1 d0 Timeout Mode Bit 0
* For Type, "R/W" = Read Write, "R" = Read Only ** TIMSET1 0 0 1 1 TIMSET0 0 1 0 1 TIMEOUT MODE Timeout Disabled (Default) Timeout After 30ms Timeout After 15ms Timeout After 7.5ms d1 Reserved d0 Reserved R R
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Register 3 (03h)
TYPE* DESCRIPTION R R Not Used Not Used BIT NAME d7 Bus 1 FET State TYPE* DESCRIPTION R/W Sets and indicates state of FET switches connected to downstream bus 1 0 = switch open (default) 1 = switch closed R/W Sets and indicates state of FET switches connected to downstream bus 2 0 = switch open (default) 1 = switch closed R R R Not Used Not Used Indicates logic state of downstream bus 1; only valid when disconnected from upstream bus 0 = SDA1, SCL1 or both are below 1V 1 = SDA1 and SCL1 are both above 1V Indicates logic state of downstream bus 2; only valid when disconnected from upstream bus 0 = SDA2, SCL2 or both are below 1V 1 = SDA2 and SCL2 are both above 1V Not Used Not Used R/W Sets logic requirements for downstream buses to be connected to upstream bus 0 = Bus Logic State bits (see register 3) of buses to be connected must be high for connection to occur (default) 1 = Connect regardless of downstream logic state R R Not Used Not Used d6 Bus 2 FET State d5 Reserved d4 Reserved d3 Bus 1 Logic State R/W Enable Mass Write Address using address (1011 110)b 0 = Disable Mass Write 1 = Enable Mass Write (default) R/W Stuck Low Timeout Set Bit 1** R/W Stuck Low Timeout Set Bit 0** d2 Bus 2 Logic State R * For Type, "R/W" = Read Write, "R" = Read Only These bits are meant to give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a "don't care" if its associated downstream bus is already connected to the upstream bus.
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LTC4305
OPERATIO
The LTC4305 is a 2-channel 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Masters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4305 to neither, either or both of the 2 downstream buses. Masters can also program the LTC4305 to disconnect the upstream bus from the downstream buses if the bus is stuck low. Undervoltage Lockout (UVLO) and ENABLE Functionality The LTC4305 contains undervoltage lockout circuitry that maintains all of its SDA, SCL and ALERT pins in high impedance states until the device has sufficient VCC supply voltage to function properly. It also ignores any attempts to communicate with it via the 2-wire buses in this condition. When the ENABLE pin voltage is low (below 0.8V), all control bits are reset to their default high impedance states, and the LTC4305 ignores 2-wire bus commands. However, with ENABLE low, the LTC4305 still monitors the ALERT1-ALERT2 pin voltages and pulls the ALERT pin low if any of ALERT1-ALERT2 is low. When ENABLE is high, devices can read from and write to the LTC4305. Connection Circuitry Masters on the upstream SDAIN/SCLIN bus can write to the Bus 1 FET State and Bus 2 FET State bits of register 3 to connect to any combination of downstream channels. By default, the Connection Circuitry shown in the block diagram will only connect to downstream channels whose corresponding Bus Logic State bits in register 3 are high at the moment that it receives the connection command. If the LTC4305 is commanded to connect to multiple channels at once, it will only connect to the channels that are high. This prevents the master on the upstream bus from connnecting to a downstream channel that may be
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stuck low. Masters can override this feature by setting the Connection Requirement Bit of register 2 high. With this bit high, the LTC4305 executes connection commands without regard to the logic states of the downstream channels. Upon receiving the connection command, the Connection Circuitry shown in the block diagram will activate the Upstream-Downstream Buffers under two conditions: first, the master must be commanding connection to one or more downstream channels, and second, there must be no stuck low condition (see "Stuck Low Timeout Fault" discussion that follows). If the connection command is successful, the Upstream-Downstream Buffer circuitry passes signals between the upstream bus and the connected downstream buses. The LTC4305 also turns off its N-channel MOSFET open-drain pull-down on the READY pin, so that READY can be pulled high by its external pullup resistor. Upstream-Downstream Buffers Once the Upstream-Downstream Buffers are activated, the functionality of the SDAIN and any connected downstream SDA pins is identical. A low forced on any connected SDA pin at any time results in all pins being low. External devices must pull the pin voltages below 0.4V worst-case with respect to the LTC4305's ground pin to ensure proper operation. The SDA pins enter a logic high state only when all devices on all connected SDA pins force a high. The same is true for SCLIN and the connected downstream SCL pins. This important feature ensures that clock stretching, clock arbitration and the acknowledge protocol always work, regardless of the how the devices in the system are connected to the LTC4305. The Upstream-Downstream Buffers provide capacitive isolation between SDAIN/SCLIN and the downstream connected buses. Note that there is no capacitive isolation between connected downstream buses; they are only
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LTC4305
OPERATIO
separated by the series combination of their switches' on resistances. While neither, either or both downstream buses may be connected at the same time, logic high levels are corrupted if both downstream buses are active and both the VCC voltage and one downstream bus pull-up voltage are larger than the pull-up supply voltage of the other downstream bus. An example of this issue is shown in Figure 1. During logic highs, DC current flows from VBUS1 through the series combination of R1, N1, N2 and R2 and into VBUS2, causing the SDA1 voltage to drop and current to be sourced into VBUS2. To avoid this problem, do not activate bus 1 when bus 2 is active.
VCC = VBUS1 = 5V
Figure 1. Example of Unacceptable Level Shifting
Rise Time Accelerators The Upstream Accelerators Enable and Downstream Accelerators Enable bits of register 1 activate the upstream and downstream rise time accelerators, respectively. When activated, the accelerators turn on in a controlled manner and source current into the pins during positive bus transitions. When no downstream buses are connected, an upstream accelerator turns on when its pin voltage exceeds 0.8V and is rising at a minimum slew rate of 0.8V/s. When one or more downstream buses are connected, the accelerator on a given pin turns on when these conditions are met:
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first, the pin's voltage is rising at a minimum slew rate of 0.8V/s; second, the voltages on both the upstream bus and the connected downstream buses exceed 0.8V. Note that a downstream bus must be connected to the upstream bus in order for its rise time accelerator current to be active. See the Applications Section for choosing a bus pull-up resistor value to ensure that the rise time accelerator switches turn on. Do not activate boost currents on a bus whose pull-up supply voltage VBUS < VCC. Doing so would cause the boost currents to source current from VCC into the VBUS supply during rising edges. Downstream Bus Connection Fault By default, the LTC4305 will only connect to downstream buses whose SDA and SCL pins are both high (above 1V) at the moment that it receives the connection command. In this case, the LTC4305 sets the Failed Connection Attempt bit of register 0 low and pulls the ALERT low when the master tries to connect to a low downstream bus. Note that users can write a high to the Connection Requirement bit of register 2 to program the LTC4305 to connect to downstream buses regardless of their logic state at the moment of connection. In this case, the Downstream Channel Connection Fault never occurs. Stuck Low Timeout Fault The Stuck Low Timeout Circuitry monitors the two common internal nodes of the downstream SDA and SCL switches and runs a timer whenever either of the internal node voltages is below 0.52V. The timer is reset whenever both internal node voltages are above 0.6V. If the timer ever reaches the time programmed by Timeout Mode Bits 1 and 0 of register 2, the LTC4305 pulls ALERT low and
SDA1 N1 VBUS2 = 2.5V R2 10k
4305 F01
R1 10k
SDA2 N2
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LTC4305
OPERATIO
disconnects the downstream buses from the upstream bus by de-biasing the Upstream-Downstream Buffers. Note that the downstream switches remain in their existing state. The Timeout Real Time bit of register 0 indicates the real-time status of the stuck low situation. The Latched Timeout Bit of register 0 is a latched bit that is set high when a timeout occurs. External Faults on the Downstream Channels When a slave on downstream channel 1 pulls the ALERT1 pin below 1V, the LTC4305 passes this information to master on the upstream bus by pulling the ALERT pin low. The functionality is the same for the slaves on downstream channel 2 and the ALERT2 pin. Each channel has its own dedicated fault bit in Register 0, so that masters can read Register 0 to determine which channels have faults. ALERT Functionality and Fault Resolution When a fault occurs, the LTC4305 pulls the ALERT pin low, as described previously. The procedure for resolving faults depends on the type of fault. If a master on the upstream bus is communicating with devices on a downstream bus via the upstream-downstream buffer circuitry-- channel 1, for example--and a device on this bus pulls the ALERT1 pin low, the LTC4305 acts transparently, and the master communicates directly with the device that caused the fault via the Upstream-Downstream Buffer circuitry to resolve the fault. In all other cases, the LTC4305 communicates with the master to resolve the fault. After the master broadcasts the Alert Response Address (ARA), the LTC4305 will respond with its address on the SDAIN line and release the ALERT pin. The ALERT line will also be released if the LTC4305 is addressed by the master. The ALERT signal will not be pulled low again until a different type of fault has occurred or the original fault is cleared and has occurred again. Figure 2 shows the details of how the fault latches and ALERT pin are set and reset. The Downstream Bus Connection Fault and faults that
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FAULT ON DISCONNECTED DOWNSTREAM BUS DOWNSTREAM BUS CONNECTION FAULT VCC D WRITE REGISTER 0 ADDRESS LTC4305 LTC4305 RESPONDS TO ARA STUCK BUS VCC D WRITE REGISTER 0 Q Q ALERT RD FAULT ON CONNECTED DOWNSTREAM BUS RD
4305 F02
Figure 2. Setting and Resetting the ALERT Pin
occur on unconnected downstream buses are grouped together and generate a single signal to drive ALERT. The Stuck Low Timeout Fault has its own dedicated pathway to ALERT; however, once a stuck low occurs, another one will not occur until the first one is cleared. For these reasons, once the master has established the LTC4305 as the source of the fault, it should read register 0 to determine the specific problem, take action to solve the problem, and clear the fault promptly. All faults are cleared by writing a dummy databyte to register 0, which is a readonly register. For example, assume that a fault occurs, the master sends out the ARA, and the LTC4305 successfully writes its address onto SDAIN and releases its ALERT pin. The master reads register 0 and learns that the ALERT2 logic state bit is low. The master now knows that a device on downstream bus 2 has a fault and writes to register 3 to connect to bus 2, so that it can communicate with the source of the fault. At this point, the master writes to register 0 to clear the fault. I2C Device Addressing Twenty-seven distinct bus addresses are configurable using the three state ADR0, ADR1 and ADR2 pins. Table 1 shows the correspondence between pin states and addresses. Note that address bits a6 and a5 are internally configured to 1 and 0, respectively. In addition, the LTC4305 responds to two special addresses. Address (1011 110) is a mass write used to write all LTC4305's,
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LTC4305
OPERATIO
regardless of their individual address settings. The mass write can be masked by setting the mass write enable bit of register 2 to zero. Address (0001 100) is the SMBus Alert Response Address. Figure 3 shows data transfer over a 2-wire bus. Supported Commands Users must write to the LTC4305 using the SMBus Write Byte protocol and read from it using the Read Byte protocol. During fault resolution, the LTC4305 also supports the Alert Response Address protocol. The formats for these protocols are shown in Figure 4. Users must follow the Write Byte protocol exactly to write to the LTC4305; if a Repeated Start Bit is issued before a Stop Bit, the LTC4305 ignores the attempted write, and its control bits remain in their preexisting state. When users follow the WriteByte protocol exactly, the new data contained in the Data Byte is written into the register selected by r1 and r0 on the Stop Bit.
SDA
SCL S
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Glitch Filters The LTC4305 provides glitch filters on the SDAIN and SCLIN pins as required by the I2C Fast Mode (400kHz) Specification. The filters prevent signals of up to 50ns (minimum) time duration and rail-to-rail voltage magnitude from passing into the two-wire bus digital interface circuitry. Fall Time Control Per the I2C Fast Mode (400kHz) Specification, the two-wire bus digital interface circuitry provides fall time control when forcing logic lows onto the SDAIN bus. The fall time always meets the limits: (20 + 0.1 * CB) < tf < 300ns where tf is the fall time in ns and CB is the equivalent bus capacitance in pF. Whenever the upstream-downstream buffer circuitry is active, its output signal will meet the fall time requirements, provided that its input signal meets the fall time requirements.
d7 - d0 a6 - a0 d7 - d0 1-7 8 9 1-7 8 9 1-7 8 9 P START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION
4305 F03
Figure 3. Data Transfer Over I2C/SMBus
1 START
7 10 a4 - a0 SLAVE ADDRESS
1 WR 0
1 ACK S 0
8 XXXXXX r1 r0 REGISTER
1 ACK S 0
8 d7 - d0 DATA BYTE
1 ACK S 0
1 STOP
WRITE BYTE PROTOCOL 1 START 7 10 a4 - a0 SLAVE ADDRESS 1 WR 0 1 ACK S 0 8 XXXXXX r1 r0 REGISTER 1 ACK S 0 1 START 7 10 a4 - a0 SLAVE ADDRESS 1 RD 1 1 ACK S 0 8 d7 - d0 DATA BYTE 1 ACK M 1 1 STOP
READ BYTE PROTOCOL 1 S 7 0001 100 1 Rd 1 1 ACK S 0 8 DEVICE ADDRESS 1 ACK M 1
4305 F04
1 P
ALERT RESPONSE ADDRESS PROTOCOL
Figure 4. Protocols Accepted by LTC4305
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LTC4305
OPERATIO
DESCRIPTION Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Table 1. LTC4305 I2C Device Addressing
HEX DEVICE ADDRESS h BC 19 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 a6 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BINARY DEVICE ADDRESS a4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 a3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 a2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 a1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 a0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R/W 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X ADR2 X X L L L L L L L L NC NC NC NC NC NC NC NC H H H H H H H H H L NC LTC4305 ADDRESS PINS ADR1 X X NC H NC NC L H L L NC H NC NC L H L L NC H NC NC L H L L H H H ADR0 X X L NC NC H L H NC H L NC NC H L H NC H L NC NC H L H NC H L L L
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LTC4305
APPLICATIO S I FOR ATIO
Design Example
A typical LTC4305 application circuit is shown in Figure 5. The circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the LTC4305. In this application, the LTC4305 VCC voltage and downstream bus 1 are powered from 3.3V, downstream bus 2 is powered from 5V, and the upstream bus is powered from 2.5V. The following sections describe a methodology for choosing the external components in Figure 5. SDA, SCL Pull-Up Resistor Selection The pull-up resistors on the SDA and SCL pins must be strong enough to provide a minimum of 100A pull-up current, per the SMBus Specification. In most systems, the required minimum strength of the pull-up resistors is determined by the minimum slew requirement to guarantee that the LTC4305's rise time accelerators are activated during rising edges. At the same time, the pull-up value should be kept low to maximize the logic low noise margin and minimize the offset voltage of the Upstream-Downstream Buffer circuitry. The LTC4305 is designed to function for a maximum DC pull-up current of 4mA. If multiple downstream channels are active at the same time, this means that the sum total of the pull-up currents from these channels must be less than 4mA. At supply voltages of 2.7V and 5.5V, pull-up resistor values of 10k work well for capacitive loads up to 215pF and 420pF, respectively.
VBACK = 2.5V
R1 10k MICROCONTROLLER
R2 10k
R3 10k 5 3 2 SCLIN SDAIN ALERT
10 9 8 4
Figure 5. A Level Shifting Circuit
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For larger bus capacitances, refer to equation (1) below. The LTC4305 works with capacitive loads up to 2nF. Assume in Figure 5 that the total parasitic bus capacitance on SDA1 due to trace and device capacitance is 100pF. To ensure that the boost currents are active during rising edges, the pull-up resistor must be strong enough to cause the SDA1 pin voltage to rise at a rate of 0.8V/s as the pin voltage is rising above 0.8V. The equation is:
ns ( VBUSMIN - 0 . 8 V) * 1250 V (1) RPULL -UP,MAX [k ] = CBUS [pF ]
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where VBUSMIN is the minimum operating pull-up supply voltage, and CBUS is the bus parasitic capacitance. In our example, VBUS1 = VCC = 3.3V, and assuming 10% supply tolerance, VBUS1MIN = 2.97V. With CBUS = 100pF, RPULL-UP,MAX = 27.1k. Therefore, we must choose a pull-up resistor smaller (i.e., stronger pull-up) than 27.1k, so a 10k resistor works fine. ALERT and READY Component Selection The pull-up resistors on the ALERT and READY pins must provide a maximum pull-up current of 3mA, so that the LTC4305 is capable of holding the pins at logic low voltages below 0.4V.
VCC = VBUS1 = 3.3V C1 0.01F 7 VCC SCL1 SDA1 ALERT1 12 13 14 SFP MODULE #1 ADDRESS = 1111 000 LTC4305 ADR2 ADR1 ADR0 GND SCL2 SDA2 ALERT2 R7 10k R8 10k VBUS2 = 5V R9 10k SFP MODULE #2 ADDRESS = 1111 001
4305 F05
R4 10k
R5 10k
R6 10k
16 15 1
ADDRESS = 1000 100
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LTC4305
APPLICATIO S I FOR ATIO
Level Shifting Considerations
In Figure 5, the LTC4305 VCC voltage is less than or equal to both of the downstream bus pull-up voltages, so both downstream buses can be active at the same time. Likewise, the rise time accelerators can be turned on for the downstream buses, but must never be activated on SCLIN and SDAIN, because doing so would result in significant current flow from VCC to VBACK during rising edges. Other Application Circuits Figure 6 illustrates how the LTC4305 can be used to expand the number of devices in a system by using nested addressing. Each I/O card contains a temperature sensor having device address 1001 000. If both I/O cards were plugged directly into the backplane, the two sensors would require two unique addresses. However, if masters use the LTC4305 in multiplexer mode, where only one downstream channel is connected at a time, then each I/O card can have a device with address 1001 000 and no problems will occur. Figures 7 and 8 show two different methods for hotswapping I/O cards onto a live two-wire bus using the LTC4305. The circuitry of Figure 7 consists of an LTC4305 residing on the edge of an I/O card having two separate downstream buses. Connect a 200k resistor to ground
VCC
R1 10k MICROCONTROLLER
R2 10k
R3 10k
VCC OPEN
Figure 6. Nested Addressing Application
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from the ENABLE pin and make the ENABLE pin the shortest pin on the card connector, so that the ENABLE pin remains at a constant logic low while all other pins are connecting. This ensures that the LTC4305 remains in its default high impedance state and ignores connection transients on its SDAIN and SCLIN pins until they have established solid contact with the backplane 2-wire bus. In addition, make sure that the ALERT card connector pin is shorter than the VCC pin, so that VCC establishes solid contact with the I/O card pull-up supply pin and powers the pull-up resistors on ALERT1-ALERT2 before ALERT makes contact. Figure 8 illustrates an alternate SDA and SCL hotswapping technique, where the LTC4305 is located on the backplane and an I/O card plugs into downstream channel 2. Before plugging and unplugging the I/O card, make sure that channel 2's downstream switch is open, so that it does not disturb any 2-wire transaction that may be occurring at the moment of connection/disconnection. Note that pull-up resistor R10 on ALERT2 should be located on the backplane and not the I/O card to ensure proper operation of the LTC4305 when the I/O card is not present. The pullup resistors on SCL2 and SDA2--R8 and R9, respectively--may be located on the I/O card, provided that downstream bus 2 is never activated when the I/O card is not present. Otherwise, locate R8 and R9 on the backplane.
C1 0.01F R4 10k 5 3 6 2 11 10 9 8 4 SCLIN SDAIN ENABLE ALERT READY ADR2 ADR1 ADR0 GND ADDRESS = 1010 000 SCL2 SDA2 ALERT2 16 15 1 LTC4305 R8 10k R9 10k 7 VCC 12 13 14 TEMPERATURE SENSOR ADDRESS = 1001 000 I/O CARD #1 R10 10k TEMPERATURE SENSOR ADDRESS = 1001 000 I/O CARD #2
4305 F06
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R5 10k
R6 10k
R7 10k
SCL1 SDA1 ALERT1
LTC4305
APPLICATIO S I FOR ATIO
VCC
R1 10k
R2 10k 5 SCLIN SDAIN ENABLE
MICROCONTROLLER VCC
VCC R3 10k
VCC 10 9 8 4 ADR2 ADR1 ADR0 GND
4305 F07
OPEN
BACKPLANE
BACKPLANE CONNECTOR
CARD CONNECTOR
Figure 7. Hot-Swapping Application
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C1 0.01F 7 VCC 12 13 14 R5 10k R6 10k R7 10k CARD_SCL1 CARD_SDA1 CARD_ALERT1# SCL1 SDA1 ALERT1 3 6 R4 200k 2 ALERT LTC4305 R11 10k VBUS2 16 15 1 R8 10k R9 10k R10 10k CARD_SCL2 CARD_SDA2 CARD_ALERT2# SCL2 SDA2 ALERT2 READY 11 ADDRESS = 1010 000
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LTC4305
PACKAGE DESCRIPTIO U
DHD Package 16-Lead Plastic DFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1707)
0.70 0.05 4.50 0.05 3.10 0.05 2.44 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.34 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 0.10 (2 SIDES) R = 0.20 TYP R = 0.115 TYP 9 16 0.40 0.10 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 0.05 4.34 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD 1 0.25 0.05 0.50 BSC 2.44 0.10 (2 SIDES) PIN 1 NOTCH
(DHD16) DFN 0504
0.00 - 0.05
NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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LTC4305
PACKAGE DESCRIPTIO U
GN Package 16-Lead Narrow Plastic SSOP
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.0165 .0015
.150 - .157** (3.810 - 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10)
.007 - .0098 (0.178 - 0.249) 0 - 8 TYP
.0532 - .0688 (1.35 - 1.75)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC4305
TYPICAL APPLICATIO
R1 10k
MICROCONTROLLER
RELATED PARTS
PART NUMBER LTC1380/LTC1393 LTC1427-50 LTC1623 LTC1663 LTC1694/LTC1694-1 LT1786F LTC1695 LTC1840 LTC4300A-1/LTC4300A-2 LTC4300A-3 LTC4301 LTC4301L LTC4302-1/LTC4302-2 LTC4303/LTC4304 LTC4306 DESCRIPTION Single-Ended 8-Channel/Differential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface Dual High Side Switch Controller with SMBus Interface SMBus Interface 10-Bit Rail-to-Rail Micropower DAC SMBus Accelerator SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer Supply Independent Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation Addressable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery 4-Channel 2-Wire Multiplexer with Capacitance Buffering COMMENTS Low RON: 35 Single-Ended/70 Differential, Expandable to 32 Single or 16 Differential Channels Precision 50A 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale 8 Selectable Addresses/16-Channel Capability DNL < 0.75LSB Max, 5-Lead SOT-23 Package Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75 PMOS 180mA Regulator, 6-Bit DAC Two 100A 8-Bit DACs, Two Tach Inputs, Four GPI0 Isolates Backplane and Card Capacitances Provides Level Shifting and Enable Functions Supply Independent Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN Address Expansion, GPIO, Software Controlled Provides Automatic Clocking to Free Stuck I2C Busses 4 Selectable Downstream Buses, Stuck Bus Disconnect, Rise Time Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
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ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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VCC C1 0.01F R2 10k R3 10k R4 10k VCC SCLIN SDAIN ENABLE ALERT READY LTC4305 VCC2 VCC ADR2 OPEN ADR1 ADR0 GND ADDRESS = 1010 000 SCL2 SDA2 ALERT2 VOLTAGE MONITOR I/O CARD
4305 F08
R5 10k
R6 10k
R7 10k
SCL1 SDA1 ALERT1 TEMPERATURE SENSOR
R8 10k
R9 10k
R10 10k
Figure 8. Alternate Hot-Swapping Application
LT/LWI/TP 0805 500 * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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